1. Field of the Invention
The present invention relates to a microcomputer capable of determining an accident of an I/O port or an external circuit for the microcomputer which is connected with the I/O port, and protecting the I/O port.
2. Description of the Background Art
FIG. 11 is a block diagram showing the structure of a conventional microcomputer described in Japanese Patent Laying-Open Gazette No. 6-12292 (1994), for example. The microcomputer 10 includes a central processing unit (hereinafter referred to as a CPU) 11, an interrupt control circuit 12, an I/O port 13, an address/data bus 14, and a port 15.
The CPU 11 is adapted to execute an instruction supplied from an external circuit (not shown) for the microcomputer 10, or a memory (not shown) stored therein. The interrupt control circuit 12 outputs an interrupt processing request signal S12 to the CPU 11 when a signal S3 is received from the I/O port 13 while the CPU 11 executes a job, thereby authorizing interruption of another processing instruction. The I/O port 13 inputs/outputs a signal between the CPU 11 and the external circuit for the microcomputer 10. The address/data bus 14 is a line which connects the CPU 11, the I/O port 13 and the like with each other for transferring addresses and data. The port 15 is a terminal of the I/O port 13 which is connected with the external circuit for inputting/outputting a signal S4 between the I/O port 13 and the external circuit.
FIG. 12 is a block diagram showing the structure of the conventional I/O port 13. A port latch 21 is supplied with a write clock signal .phi.pw from the address/data bus 14. The port latch 21 holds data S5 transferred through the address/data bus 14 in response to the clock signal .phi.pw. Data S6 held by the port latch 21 is supplied to an input terminal of an output buffer 23 through a signal line 100. An output terminal of the output buffer 23 is connected with the port 15 by a signal line 101, so that the output buffer 23 serves as an element for outputting the data S6 held by the port latch 21 from the port 15 as a signal S4. An input terminal of an input buffer 24 is also connected to the output terminal of the output buffer 23 by the signal line 100, so that the input buffer 24 serves as an element for incorporating data S4 inputted from the external circuit through the port 15 in the microcomputer 10. A read-in buffer 25 is an element for supplying a signal S7 outputted from the input buffer 24 to the circuits present in the interior of the microcomputer 10 excluding the I/O port 13. An output terminal of the read-in buffer 25 is connected to the address/data bus 14. An exclusive OR circuit (hereinafter referred to as an EX-OR gate) 26 is adapted to compare the data S6 held by the port latch 21 with the signal S7 outputted from the input buffer 24. Therefore, an input terminal of the EX-OR gate 26 is connected to the signal line 100, while another input terminal thereof is connected to the output terminal of the input buffer 24 through a signal line 102. An output terminal of the EX-OR gate 26 is connected to a latch 22 through a signal line 103. The latch 22 is supplied with a write clock signal .phi. from the address/data bus 14. The latch 22 temporarily holds an output signal S8 of the EX-OR gate 26 in synchronization with rise of the clock signal .phi..
FIG. 13A-FIG. 13G are timing charts showing operation timings of the respective parts in the conventional microcomputer 10 shown in FIG. 12. The operation of the I/O port 13 shown in FIG. 12 is now described with reference to FIG. 13A-FIG. 13G. FIG. 13A-FIG. 13G show signals .phi., .phi..sub.pw, S6, S4, S5, S7, S3, respectively.
An operation in case of writing logical data "0" in the port latch 21 as the data S5 is first described (hereinafter logical data is expressed in "0" or "1").
When the external circuit is normal, the port latch 21 outputs "0", which is the data S6 held therein, to the output buffer 23 and the EX-OR gate 26 at a period T1, as shown in FIG. 13C. Thus, the output buffer 23 outputs "0" to the port 15 as the signal S4.
On the other hand, the EX-OR gate 26 outputs "0" as the signal S8, while the signal S3 outputted from the latch 22 becomes "0" as shown in FIG. 13G.
An operation performed when the external circuit short-circuits with a power supply line and the logical level of the port 15 changes to "1" to differ from the data S6 held by the port latch 21, for example, is now described. In this case, the value of the signal S8 outputted from the EX-OR gate 26 becomes "1", and the signal S3 outputted from the latch 22 becomes "1" in a period T2, as shown in FIG. 13G. This means that some accident takes place in the port 15.
When such an accident takes place, "1" is inputted in the interrupt control circuit 12 by the signal S3 outputted from the latch 22. The interrupt control circuit 12 outputs the interrupt processing request signal S12 to the CPU 11. Due to the supply of the interrupt processing request signal S12, the CPU 12 recognizes the occurrence of the accident in the port 15 of the I/O port 13, and starts prescribed interrupt processing.
An operation in case of writing the data S5 of "1" in the port latch 21 can also be explained similarly to the case where the data S5 written in the port latch 21 is "0".
When the external circuit is normal, the port latch 21 outputs "1" to the output buffer 23 and the EX-OR gate 26 as the held data S6 in a period T3, as shown in FIG. 13C. Since "0" is inputted in the input terminal of the output buffer 23, the output buffer 23 outputs "1" to the port 15 and the EX-OR gate 26 as the signal S4, as shown in FIG. 13D. The values of both input terminals of the EX-OR gate 26 become "1" together, whereby the EX-OR gate 26 outputs "0" as the signal S8, so that the value of the output signal S3 from the latch 22 becomes "0".
When the external circuit short-circuits with an earthing wire and the value of the signal S4 at the port 15 changes to "1", for example, the value of the signal S8 outputted from the EX-OR gate 26 becomes "1", and the value of the signal S3 outputted from the latch 22 becomes "1" in a period T4, as shown in FIG. 13G.
FIG. 14 is a circuit diagram showing another mode of the structure of a conventional I/O port 13. In the structure of the I/O port 13 shown in FIG. 14, an invertor 27 and an AND gate 28 are further added to the I/O port 13 shown in FIG. 12. Namely, the I/O port 13 shown in FIG. 14 is so structured that a clock signal .phi.pw is inputted in one input terminal of the AND gate 28 and an output signal S3 of a latch 22 is inverted by the invertor 27 and inputted in another input terminal of the AND gate 28.
When an accident takes place in an external circuit (not shown) which is connected to the port 15 and the value of the signal S3 outputted from the latch 22 is "1", the invertor 27 and the AND gate 28 inhibit further writing in a port latch 21.
Due to such write inhibit processing for the port latch 21, it is possible to prevent the port latch 21 from data rewriting and disappearance of the result of detection of the accident on the port 15 in the period when a CPU 11 is notified of the accident detection and recognizes the occurrence of the accident for performing self processing.
FIG. 15 is a graph showing the relations between voltages and logical levels of the port 15. With reference to FIG. 15, the mode of the port 15 upon occurrence of a short-circuit accident in the external circuit for the microcomputer is described. Referring to FIG. 15, the axis of abscissas shows times, and the axis of ordinates shows voltages.
When the external circuit connected to the port 15 is formed by only CMOS elements and its source voltage is expressed as Vcc, the logical levels are set at "0", "1" and undetermined when the voltages of the port 15 are 0 V to 0.2 Vcc, 0.8 Vcc to Vcc and 0.2 Vcc to 0.8 Vcc respectively, for example. Referring to FIG. 15, numerals 200 and 201 denote the ranges where the external circuit is at the logical levels of "1" and "0" respectively.
When the external circuit is formed by only bipolar elements, on the other hand, the logical levels are at "0", "1" and undetermined when the voltages of the port 15 are 0 V to 0.16 Vcc, 0.5 Vcc to Vcc and 0.16 Vcc to 0.5 Vcc respectively, for example. Referring to FIG. 15, numerals 202 and 203 denote the ranges of the logical levels of "1" and "0" respectively.
Assuming that a short-circuit accident takes place between an external circuit which is formed by only CMOS elements and a power supply line and the voltage level of the port 15 belongs to the logical level of "0" in the initial stage of the occurrence of the accident, for example, the voltage of the port 15 is increased toward the source voltage Vcc with time through various paths as shown by curves L1 to L3 in FIG. 15, since short-circuit resistance varies with the degree of the short-circuit accident.
Assuming that only one input buffer 24 serving as a logical level detector having a logical threshold value of 0.5 Vcc in a circuit for detecting the logical level of the port 15, the short-circuit accident cannot be confirmed when the voltage of the port 15 stays at a level of about 0.3 Vcc to 0.4 Vcc in the region as in the example shown by the curve L2 or L3, for example, since the voltage level of the port 15 is not in excess of 0.5 Vcc, which is the logical threshold value of the logical level detector.
Similarly, when the voltage of the port 15 belongs to the logical level of "1" in the initial stage of occurrence of an accident while the port 15 short-circuits with an earthing wire in the external circuit and the voltage of the port 15 is reduced to and stays at about 0.6 Vcc as in an example shown by a curve L6, the short-circuit accident cannot be confirmed.
In the I/O port 13 shown in FIG. 14, the invertor 27 and the AND gate 28 are added so that an interrupt signal S3 is generated toward the CPU 11 when an accident is found in the port 15 while writing from the CPU 11 to the port latch 21 is simultaneously inhibited, thereby preventing confirmation of the occurrence of the accident from disappearance.
According to this method, however, a high current flows from the port 15 to the external circuit causing the short-circuit accident in a time up to accident processing to break transistors of the output buffer 23, since output of the output buffer 23 is not inhibited.
On the other hand, there has been such a demand that the output buffer 23 is not erroneously connected to the external circuit when a short-circuit accident takes place in case where runaway of the microcomputer 10 is derived by an accident.